? semiconductor components industries, llc, 2013 january, 2013 ? rev. 0 1 publication order number: NCP45524/d NCP45524, ncp45525 ecoswitch advanced load management controlled load switch with low r on the ncp4552x series of load switches provide a component and area-reducing solution for efficient power domain switching with inrush current limit via soft start. these devices are designed to integrate control and driver functionality with a high performance low on ? resistance power mosfet in a single package. this cost effective solution is ideal for power management and hot-swap applications requiring low power consumption in a small footprint. features ? advanced controller with charge pump ? integrated n-channel mosfet with low r on ? input voltage range 0.5 v to 13.5 v ? soft-start via controlled slew rate ? adjustable slew rate control (ncp45525) ? power good signal (NCP45524) ? extremely low standby current ? load bleed (quick discharge) ? this is a pb ? free device typical applications ? portable electronics and systems ? notebook and tablet computers ? telecom, networking, medical, and industrial equipment ? set ? top boxes, servers, and gateways ? hot swap devices and peripheral ports figure 1. block diagram (*note: either pg or sr available for each part) en bandgap & biases charge pump delay and slew rate control gnd bleed sr* control logic pg* v out v in v cc dfn8, 2x2 case 506cc marking diagram http://onsemi.com r on typ v cc i max 18.0 m 3.3 v 6 a 3.3 v 18.8 m v in 1.8 v 5.0 v pin configuration (top view) see detailed ordering and shipping information on page 10 of this data sheet. ordering information 1 xx = 4h for NCP45524 ? h = 4l for NCP45524 ? l = 5h for ncp45525 ? h = 5l for ncp45525 ? l m = date code = pb ? free package xx m 1 (note: microdot may be in either location) 21.9 m 3.3 v 12 v 1 pg or sr en gnd bleed 4 2 3 8 7 6 5 9: v in v out v out v cc v in
NCP45524, ncp45525 http://onsemi.com 2 table 1. pin description pin name function 1, 9 v in drain of mosfet (0.5 v ? 13.5 v), pin 1 must be connected to pin 9 2 en NCP45524 ? h & ncp45525 ? h ? active ? high digital input used to turn on the mosfet, pin has an internal pull down resistor to gnd NCP45524 ? l & ncp45525 ? l ? active ? low digital input used to turn on the mosfet, pin has an internal pull up resistor to v cc 3 v cc supply voltage to controller (3.0 v ? 5.5 v) 4 gnd controller ground 5 bleed load bleed connection; tie to gnd if not used 6 pg NCP45524 ? active ? high, open ? drain output that indicates when the gate of the mosfet is fully charged, external pull up resistor 1 k to an external voltage source required; tie to gnd if not used sr ncp45525 ? slew rate adjustment; float if not used 7, 8 v out source of mosfet connected to load table 2. absolute maximum ratings rating symbol value unit supply voltage range v cc ? 0.3 to 6 v input voltage range v in ? 0.3 to 18 v output voltage range v out ? 0.3 to 18 v en digital input range v en ? 0.3 to (v cc + 0.3) v pg output voltage range (note 1) v pg ? 0.3 to 6 v thermal resistance, junction ? to ? ambient, steady state (note 2) r ja 40.0 c/w thermal resistance, junction ? to ? ambient, steady state (note 3) r ja 72.7 c/w thermal resistance, junction ? to ? case (v in paddle) r jc 5.3 c/w continuous mosfet current @ t a = 25 c i max 6.0 a total power dissipation @ t a = 25 c (notes 2 and 4) derate above t a = 25 c p d 2.50 24.9 w mw/ c total power dissipation @ t a = 25 c (notes 3 and 4) derate above t a = 25 c p d 1.37 13.8 w mw/ c storage temperature range t stg ? 40 to 150 c lead temperature, soldering (10 sec.) t sld 260 c esd capability, human body model (notes 5 and 6) esd hbm 3.0 kv esd capability, machine model (note 5) esd mm 200 v esd capability, charged device model (note 5) esd cdm 1.0 kv latch ? up current immunity (notes 5 and 6) lu 100 ma stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. NCP45524 only. pg is an open ? drain output that requires an external pull up resistor 1 k to an external voltage source. 2. surface ? mounted on fr4 board using 1 sq ? in pad, 1 oz cu. 3. surface ? mounted on fr4 board using the minimum recommended pad size, 1 oz cu. 4. specified for derating purposes only, ensure that i max is never exceeded. 5. tested by the following methods @ t a = 25 c: esd human body model tested per jesd22 ? a114 esd machine model tested per jesd22 ? a115 esd charged device model tested per jesd22 ? c101 latch ? up current tested per jesd78 6. rating is for all pins except for v in and v out which are tied to the internal mosfet?s drain and source. t ypical mosfet esd performance for v in and v out should be expected and these devices should be treated as esd sensitive.
NCP45524, ncp45525 http://onsemi.com 3 table 3. operating ranges rating symbol min max unit supply voltage v cc 3 5.5 v input voltage v in 0.5 13.5 v ground gnd 0 v ambient temperature t a ? 40 85 c junction temperature t j ? 40 125 c table 4. electrical characteristics (t j = 25 c unless otherwise specified) parameter conditions (note 7) symbol min typ max unit mosfet on ? resistance v cc = 3.3 v; v in = 1.8 v r on 18.0 24.0 m v cc = 3.3 v; v in = 5 v 18.8 25.0 v cc = 3.3 v; v in = 12 v 21.9 31.7 leakage current (note 8) v en = 0 v; v in = 13.5 v i leak 0.1 1 a controller supply standby current (note 9) v en = 0 v; v cc = 3 v i stby 0.65 2 a v en = 0 v; v cc = 5.5 v 3.2 4.5 supply dynamic current (note 10) v en = v cc = 3 v; v in = 12 v i dyn 180 300 a v en = v cc = 5.5 v; v in = 1.8 v 475 680 bleed resistance v en = 0 v; v cc = 3 v r bleed 86 115 144 v en = 0 v; v cc = 5.5 v 72 97 121 en input high voltage v cc = 3 v ? 5.5 v v ih 2 v en input low voltage v cc = 3 v ? 5.5 v v il 0.8 v en input leakage current NCP45524 ? h; ncp45525 ? h; v en = 0 v i il 90 500 na NCP45524 ? l; ncp45525 ? l; v en = 5.5 v i ih 90 500 en pull down resistance NCP45524 ? h; ncp45525 ? h r pd 76 100 124 k en pull up resistance NCP45524 ? l; ncp45525 ? l r pu 76 100 124 k pg output low voltage (note 11) NCP45524; v cc = 3 v; i sink = 5 ma v ol 0.2 v pg output leakage current (note 12) NCP45524; v cc = 3 v; v term = 3.3 v i oh 5 100 na slew rate control constant (note 13) ncp45525; v cc = 3 v k sr 24 31 38 a 7. v en shown only for NCP45524 ? h, ncp45525 ? h (en active ? high) unless otherwise specified. 8. average current from v in to v out with mosfet turned off. 9. average current from v cc to gnd with mosfet turned off. 10. average current from v cc to gnd after charge up time of mosfet. 11. pg is an open-drain output that is pulled low when the mosfet is disabled. 12. pg is an open-drain output that is not driven when the gate of the mosfet is fully charged, requires an external pull up res istor 1 k to an external voltage source, v term . 13. see applications information section for details on how to adjust the slew rate.
NCP45524, ncp45525 http://onsemi.com 4 table 5. switching characteristics (t j = 25 c unless otherwise specified) (notes 14 and 15) parameter conditions symbol min typ max unit output slew rate (note 16) v cc = 3.3 v; v in = 1.8 v sr 11.9 kv/s v cc = 5.0 v; v in = 1.8 v 12.1 v cc = 3.3 v; v in = 12 v 13.5 v cc = 5.0 v; v in = 12 v 13.9 output turn ? on delay (note 16) v cc = 3.3 v; v in = 1.8 v t on 220 s v cc = 5.0 v; v in = 1.8 v 185 v cc = 3.3 v; v in = 12 v 270 v cc = 5.0 v; v in = 12 v 260 output turn ? off delay (note 16) v cc = 3.3 v; v in = 1.8 v t off 1.2 s v cc = 5.0 v; v in = 1.8 v 0.9 v cc = 3.3 v; v in = 12 v 0.4 v cc = 5.0 v; v in = 12 v 0.2 power good turn ? on time (note 17) v cc = 3.3 v; v in = 1.8 v t pg,on 0.91 ms v cc = 5.0 v; v in = 1.8 v 0.93 v cc = 3.3 v; v in = 12 v 1.33 v cc = 5.0 v; v in = 12 v 1.21 power good turn ? off time (note 17) v cc = 3.3 v; v in = 1.8 v t pg,off 21 ns v cc = 5.0 v; v in = 1.8 v 15 v cc = 3.3 v; v in = 12 v 21 v cc = 5.0 v; v in = 12 v 15 14. see below figure for test circuit and timing diagram. 15. tested with the following conditions: v term = v cc ; r pg = 100 k ; r l = 10 ; c l = 0.1 f. 16. applies to NCP45524 and ncp45525. 17. applies only to NCP45524. en ncp4552x ? h pg gnd bleed off on sr 10% 90% v t sr = v t 50% 50% 90% 50% 50% figure 2. switching characteristics test circuit and timing diagram v out v in v cc c l r l v term r pg t pg,off t off t pg,on t on v out v pg v en
NCP45524, ncp45525 http://onsemi.com 5 applications information enable control both the NCP45524 and the ncp45525 have two part numbers, ncp4552x-h and ncp4552x-l, that only differ in the polarity of the enable control. the ncp4552x-h devices allow for enabling the mosfet in an active-high configuration. when the v cc supply pin has an adequate voltage applied and the en pin is at a logic high level, the mosfet will be enabled. similarly, when the en pin is at a logic low level, the mosfet will be disabled. an internal pull down resistor to ground on the en pin ensures that the mosfet will be disabled when not being driven. the ncp4552x-l devices allow for enabling the mosfet in an active-low configuration. when the v cc supply pin has an adequate voltage applied and the en pin is at a logic low level, the mosfet will be enabled. similarly, when the en pin is at a logic high level, the mosfet will be disabled. an internal pull up resistor to v cc on the en pin ensures that the mosfet will be disabled when not being driven. power sequencing the ncp4552x devices will function with any power sequence, but the output turn ? on delay performance may vary from what is specified. to achieve the specified performance, there are two recommended power sequences: 1) v cc v in v en 2) v in v cc v en load bleed (quick discharge) the ncp4552x devices have an internal bleed resistor, r bleed , which is used to bleed the charge off of the load to ground after the mosfet has been disabled. in series with the bleed resistor is a bleed switch that is enabled whenever the mosfet is disabled. the mosfet and the bleed switch are never concurrently active. in order to realize this functionality, the bleed pin must be connected to v out either directly (as shown in figures 4 and 7) or through an external resistor, r ext (as shown in figures 3 and 6). r ext should not exceed 1 k and can be used to increase the total bleed resistance. care must be taken to ensure that the power dissipated across r bleed is kept at a safe level. r ext can be used to decrease the amount of power dissipated across r bleed . if the load bleed function is not desired, the bleed pin should be tied to gnd. power good the NCP45524 devices have a power good output (pg) that can be used to indicate when the gate of the mosfet is fully charged. the pg pin is an active-high, open-drain output that re quires an external pu ll up resistor, r pg , greater than or equal to 1 k to an external voltage source, v term , that is compatible with input levels of all devices connected to this pin (as shown in figures 3 and 4). the power good output can be used as the enable signal for other active ? high devices in the system (as shown in figure 5). this allows for guaranteed by design power sequencing and reduces the number of enable signals needed from the system controller. if the power good feature is not used in the application, the pg pin should be tied to gnd. slew rate control the ncp4552x devices are equipped with controlled output slew rate which provides soft start functionality. this limits the inrush current caused by capacitor charging and enables these devices to be used in hot swap applications. the slew rate of the ncp45525 can be decreased with an external capacitor added between the sr pin and ground (as shown in figures 6 and 7). with an external capacitor present, the slew rate can be determined by the following equation: slew rate k sr c sr [v s] (eq. 1) where k sr is the specified slew rate control constant, found in table 4, and c sr is the slew rate control capacitor added between the sr pin and ground. the slew rate of the device will always be the lower of the default slew rate and the adjusted slew rate. therefore, if the c sr is not large enough to decrease the slew rate more than the specified default value, the slew rate of the device will be the default value. the sr pin can be left floating if the slew rate does not need to be decreased.
NCP45524, ncp45525 http://onsemi.com 6 figure 3. NCP45524 typical application diagram ? load switch bandgap & biases charge pump delay and slew rate control control logic load controller 3.0 v ? 5.5 v power supply or battery 0.5 v ? 13.5 v gnd bleed v out v in pg en v cc r pg 100 k v term = 3.3 v r ext figure 4. NCP45524 typical application diagram ? hot swap bandgap & biases charge pump delay and slew rate control control logic load en pg gnd backplane removable card gnd bleed v out pg en v cc v in r pg v term v in 0.5 v ? 13.5 v v cc 3.0 v ? 5.5 v
NCP45524, ncp45525 http://onsemi.com 7 figure 5. NCP45524 simplified application diagram ? power sequencing with pg output pg NCP45524 ? h en controller pg NCP45524 ? h en pg r pd 100 k pg r pd 100 k r pg 10 k v term = 3.3 v figure 6. ncp45525 typical application diagram ? load switch bandgap & biases charge pump delay and slew rate control control logic load controller 3.0 v ? 5.5 v power supply or battery 0.5 v ? 13.5 v sr gnd c sr bleed v out r ext v in v cc en
NCP45524, ncp45525 http://onsemi.com 8 bandgap & biases charge pump delay and slew rate control control logic load 3.0 v ? 5.5 v en gnd backplane removable card figure 7. ncp45525 typical application diagram ? hot swap v cc en v in v cc sr gnd bleed c sr v out 0.5 v ? 13.5 v v in
NCP45524, ncp45525 http://onsemi.com 9 package dimensions dfn8 2x2, 0.5p case 506cc issue o notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.15 and 0.30 mm from terminal tip. 4. coplanarity applies to the exposed pad as well as the terminals. ?? ?? a d e b c 0.10 pin one 2x reference 2x top view side view bottom view l d2 e2 c c 0.10 c 0.10 c 0.08 a1 seating plane 8x note 3 b 8x 0.10 c 0.05 c a b b dim min max millimeters a 0.80 1.00 a1 0.00 0.05 b 0.20 0.30 d 2.00 bsc d2 1.50 1.70 e 2.00 bsc e2 0.80 1.00 e 0.50 bsc l 0.18 0.38 1 4 8 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 0.50 pitch 1.00 2.30 1 dimensions: millimeters 0.50 8x note 4 0.30 8x detail a a3 0.20 ref a3 a detail b a1 a3 ?? ??? 0.15 outline package e recommended k 0.27 ref 5 1.70 k alternate construction l1 detail a l alternate constructions l e/2 0.20
NCP45524, ncp45525 http://onsemi.com 10 ordering information device pin 6 functionality en polarity package shipping ? NCP45524imntwg ? h pg active ? high dfn8 (pb ? free) 3000 / tape & reel NCP45524imntwg ? l pg active ? low ncp45525imntwg ? h sr active ? high ncp45525imntwg ? l sr active ? low ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other intellectual property. a list ing of scillc?s product/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parame ters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 NCP45524/d ecoswitch is a trademark of semiconductor components industries, llc (scillc). literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
|
